module AGC_APP(
    input clk_60m,
    input rst_n,
    input signed [23:0] data_l,
    input signed [23:0] data_r,
    input [10:0] pos_cnt,
    
    output reg signed [15:0] AF_data_l,
    output reg signed [15:0] AF_data_r,
    output tVAD
);

//1.利用计数器构建出时序控制线
wire agc_sync = (pos_cnt == 11'd0) ? 1'b1 : 1'b0;
wire agc_data_valid = (pos_cnt == 11'd50 || pos_cnt == 11'd150) ? 1'b1 : 1'b0;

//2.数据总线
wire signed [23:0] data = (pos_cnt >= 11'd45 || pos_cnt <= 11'd55) ? data_l : data_r;

//3.例化模块
wire agc_out_data_valid;
wire signed [23:0] agc_data_o;
AGC_Top your_instance_name(
		.clk(  clk_60m  ), //input clk
		.rstn(  rst_n  ), //input rstn
		.ce(  1'b1  ), //input ce
		.sync(  agc_sync  ), //input sync
		.pdata( data ), //input [23:0] pdata
		.scale_ratio(8'h40), //input [7:0] scale_ratio,这里放大了四倍
		.require_valid( agc_data_valid ), //input require_valid
		.respond_ready(  1'b1  ), //input respond_ready
		.require_ready(       ), //output require_ready
		.tVAD(   tVAD ), //output tVAD
		.respond_valid(  agc_out_data_valid  ), //output respond_valid
		.sync_out(     ), //output sync_out
		.pdata_out(  agc_data_o  ) //output [23:0] pdata_out
);

//4.输出接口
reg switch;
always @(posedge clk_60m or negedge rst_n) begin
    if(!rst_n) begin
        switch <= 1'b0;
        AF_data_l <= 16'd0;
        AF_data_r <= 16'd0;
    end
    else if(pos_cnt == 11'd0)//每次重新采样就清零辅助计数器
        switch <= 1'b0;
    else if(agc_out_data_valid && ~switch) begin //左声道数据
        AF_data_l <= agc_data_o[23:8];
        switch <= 1'b1;
    end
    else if(agc_out_data_valid && switch) begin //右声道数据
        AF_data_r <= agc_data_o[23:8];
    end
    else begin
        AF_data_l <= AF_data_l;
        AF_data_r <= AF_data_r;
    end
end

endmodule